Condor Technology to Fly "Cuzco" RISC-V CPU into the Datacenter (www.nextplatform.com)

Condor Computing (Andes’ U.S. arm) unveiled its "Cuzco" RISC-V core as a datacenter-class, licensable CPU IP aimed at challenging Arm/x86 incumbents. Condor demonstrated full hardware emulation (booting Linux and other OSes) in July and plans to ship first customer parts in Q4. Cuzco targets the RVA-23 datacenter profile, scales to eight cores with up to 8 MB private L2 in a coherent cluster and a shared 256 MB L3, uses a 12-stage pipeline, an eight-instruction dispatch into a pooled execution backend, and a slice-based microarchitecture (pairs of pipelines grouped into up to four identical slices). The technical punch is in the scheduler and execution structure: instead of expensive CAM-backed Tomasulo scheduling, Cuzco uses a time-based issuance scheme—its register scoreboard records write times that determine future read times, while a time resource matrix (TRM) predicts when ALUs, buses and queues will be free, enabling predictive issuance and removing power/area heavy CAMs. That design aims to make wide out-of-order machines more power- and area-efficient. Backed by Andes’ extensive RISC-V IP track record (17B chips and growing revenue exposure to AI), Cuzco’s success could materially accelerate RISC-V adoption in datacenters and HPC by offering a high-performance, licensable alternative with clear efficiency trade-offs.