China claims domestically-designed 14nm logic chips can rival 4nm Nvidia silicon (www.tomshardware.com)

At the ICC Global CEO Summit in Beijing, China Semiconductor Industry Association vice chairman Wei Shaojun announced a domestically designed AI processor that he says uses mature 14nm logic bonded directly to 18nm DRAM via 3D hybrid bonding and a “software‑defined” near‑memory compute architecture. Wei claimed the stack delivers roughly 120 TFLOPS total and about 2 TFLOPS/W — figures he suggested would outclass Nvidia’s A100 and approach Hopper/Blackwell efficiency — and framed the design as a route to break China’s dependence on Nvidia’s CUDA ecosystem while keeping the supply chain fully domestic. Technically this is significant because it shifts the competitive axis from extreme node scaling to advanced packaging and memory‑proximate compute: hybrid bonding can give much denser, lower‑latency interconnects than traditional chiplets, enabling frequent memory access without the “memory wall.” But the announcement lacked benchmarks and concrete vendor names; hybrid bonded logic+DRAM raises thermal, yield and manufacturing‑precision challenges, and software‑tooling and broad framework integration (PyTorch/TensorFlow/ONNX compatibility) remain necessary to displace CUDA. If validated, the approach would be a realistic near‑term path for China to regain accelerator competitiveness under export controls; if not, the claims may reflect aspiration more than proven silicon.