After 6 years of promises and no shipping silicon, Tachyum revises CPU specs (www.tomshardware.com)

Tachyum this week published updated target specifications and performance claims for its long-promised Prodigy “universal” processor—six years after the project began and with no shipping silicon. The revised design is a multi-chiplet SiP targeted at a 2nm-class node, with up to four chiplets (768–1,024 cores), 8-way out-of-order cores with integrated matrix/vector accelerators, and per‑chiplet stacks of up to 256 usable cores arranged in a systolic-array-like topology. Top-end SKUs claim up to 1 GB of L2/L3 per chiplet, 24 memory channels per socket (48 TB DDR5-17600 claimed), 3.38 TB/s peak bandwidth per socket, PCIe 7.0 support, and headline performance numbers such as “1,000 PFLOPS on inference” and 400 FP64 TFLOPS for HPC. Tachyum even claims a rack will be ~21× faster than a Rubin‑based Nvidia NVL576 configuration. Those specs would be disruptive if real, but the announcement raises major technical and credibility flags for the AI/ML community. Moving from a planned 5nm FinFET design to a 2nm GAA process implies a near-complete RTL rewrite, long verification, multi-stage tapeout and bring‑up timelines, and development costs likely in the hundreds of millions—making realistic shipping no earlier than 2029–2032. Several claimed features (DDR5‑17600 modules, 2 TB DIMMs, extreme core counts at 6 GHz and 1,600 W power) are currently impractical, and performance claims conflict with bandwidth constraints and lack independent benchmarking. Given Tachyum’s track record, cash requirements, and fierce competition from GPUs and established CPU vendors, the community should treat these promises cautiously.