An MLIR Pipeline for Offloading Fortran to FPGAs via OpenMP (dl.acm.org)

A recent paper introduces an MLIR-based compilation pipeline that automates offloading Fortran workloads to FPGAs using OpenMP target directives. The system accepts Fortran (via the MLIR FIR front end), lowers it through MLIR’s intermediate dialects (SCF/Affine/OpenMP/LLVM or CIRCT paths), applies loop and data-layout transformations, and emits code compatible with FPGA toolchains or HLS flows. By interpreting OpenMP target and teams/parallel constructs inside MLIR, the pipeline maps compute kernels and data movement to FPGA-friendly patterns (tiling, unrolling, pipelining, explicit buffering) while preserving the high-level OpenMP portability model. This work is significant because it gives HPC and scientific Fortran code a relatively low-effort route to FPGA acceleration without manual rewrites, leveraging MLIR’s modular passes and multi-backend lowering to target both HLS and RTL toolchains. Key technical implications include reusing MLIR dialects to perform target-aware optimizations, handling Fortran-specific semantics via FIR, and bridging OpenMP’s offload model to FPGA execution paradigms. The approach highlights trade-offs—automated transformations can expose parallelism and reduce developer burden, but effective FPGA mapping still requires careful memory staging, device-host data orchestration, and backend-specific tuning—making this a pragmatic step toward broader FPGA adoption in legacy HPC ecosystems.