What if the AI race isn't about chips at all? (www.ft.com)

The piece argues that the competition driving AI progress is no longer—or perhaps never was—just about raw silicon. While GPUs, TPUs and custom accelerators supply the FLOPS needed for training, practical performance is dominated by memory capacity, bandwidth, interconnects and the software stack that orchestrates distributed training. Innovations in model architecture, optimization tricks (gradient checkpointing, ZeRO-style optimizer-state sharding), quantization and sparsity, efficient fine-tuning methods (LoRA, adapters), MoE routing, compilers and runtimes can cut compute costs and latency far more cheaply than new chip designs. Access to high-quality data, pre-trained weights, tooling and cloud APIs lets smaller teams build competitive systems without owning cutting-edge fabs. For the AI/ML community this reframing matters: technical gains will often come from systems engineering, algorithms and data curation rather than transistor-level improvements. That shifts where investment and policy should focus—on scalable data pipelines, open model ecosystems, interconnect and memory-centric hardware, efficient distributed algorithms and software stacks that squeeze more out of existing accelerators. Practically, it lowers the barrier to entry (via model distillation, quantization, and cloud-hosted instances) and emphasises bottlenecks like communication overhead, I/O, and model sharding strategies. In short, chips are necessary but not sufficient; the next leaps will likely be made by improvements across algorithms, data, and orchestration rather than silicon alone.