AMD doubles rack size for 2027 with Verano CPUs and 144 MI500 GPUs (www.techradar.com)

At its Advancing AI event AMD revealed technical details for its Zen 6 “Venice” CPU and sketched plans for a much larger 2027 AI rack. Venice is built on a 2nm process, packs up to 256 Zen 6 cores (≈33% more cores than current EPYC “Turin”) and—per AMD—delivers about 70% more compute performance. Critically for AI workloads, Venice more than doubles per-socket memory bandwidth to roughly 1.6 TB/s and adds PCIe Gen6 for faster CPU↔GPU communication, aiming to keep high-end Instinct GPUs fed with data at rack scale. Looking beyond 2026’s Helios racks (18 racks housing 72 MI400 GPUs), AMD previewed a 2027 configuration built around next‑generation Verano CPUs and MI500-series GPUs that would double capacity to 36 racks and ~144 GPUs. The Verano/MI500 platform is expected to carry forward Venice’s high-bandwidth, high-efficiency design, improving scalability, utilization and total cost of ownership for large-scale training and inference. If realized, the combination of higher memory bandwidth, faster PCIe links and denser GPU counts could substantially reduce CPU/GPU bottlenecks, raise training throughput for huge models, and tighten power/performance and cost envelopes for hyperscalers and AI cloud providers. Details remain provisional as AMD continues development.