An efficient probabilistic hardware architecture for diffusion-like models (arxiv.org)

Researchers propose an all‑transistor probabilistic computing architecture that implements denoising (diffusion‑like) models directly in hardware, addressing two key blockers of prior stochastic‑compute ideas: limited modeling expressivity and reliance on exotic, unscalable devices. Instead of simulating randomness in software or using specialized non‑CMOS components, the design leverages transistor‑level circuits to perform probabilistic sampling and denoising primitives natively. A system‑level analysis shows that prototype devices based on this architecture could match GPU throughput on a basic image benchmark while using roughly 10,000× less energy, suggesting dramatic gains for inference and sampling workloads. This work matters because diffusion and denoising models are central to modern generative AI, and energy‑efficient hardware could enable always‑on or edge generative capabilities that are currently infeasible due to power constraints. By demonstrating a CMOS‑friendly path to probabilistic computing, the paper opens a route to highly parallel, low‑power samplers for inference (and possibly parts of training) of diffusion‑style models. Key caveats: the evaluation is on a simple image benchmark and is a system‑level projection rather than large‑scale silicon results, so further work is needed to validate scalability, fidelity on complex models, and integration with full training/inference stacks.