Precise and scalable analogue matrix equation solving using resistive RAM chips (www.nature.com)

Researchers demonstrated a precise, scalable analogue matrix-equation solver implemented on foundry-fabricated 1T1R resistive RAM (RRAM) chips that combines low-precision analogue inversion with high-precision analogue matrix–vector multiplication (MVM) to perform iterative refinement entirely in the analogue domain. Using 3-bit per-cell RRAM arrays (eight conductance levels) and a block-matrix (BlockAMC) architecture, they solved medium-scale (up to 16×16) real-valued linear systems to 24-bit fixed-point accuracy (comparable to FP32) and showed that a massive MIMO signal-detection task converged to FP32-level performance in just three iterations. Benchmarking suggests potential hardware advantages of roughly 1,000× higher throughput and 100× better energy efficiency than state-of-the-art digital processors at the same precision. Key technical innovations include using a closed-loop low-precision INV (LP-INV) implemented on the most-significant 3-bit slice to produce fast approximate updates, and high-precision MVM (HP-MVM) realized by bit-slicing the full matrix across multiple RRAM arrays and combining partial products with shift-and-add. The system uses low-resolution DACs/ADCs for LP-INV and higher-precision bit-sliced HP-MVM across a 1-Mb RRAM chip, with robust TaOx 1T1R devices showing 100% 3-bit programming success across tested cells (0.5–35 μS range). By keeping matrix algebra in situ and leveraging iterative analogue refinement, the approach addresses precision and scalability limits of previous analogue INV schemes and offers a practical pathway to energy-efficient, high-throughput linear algebra accelerators that mitigate von Neumann bottlenecks.