Tenstorrent Wormhole Series (www.corsix.org)

Tenstorrent has begun shipping its Wormhole n150s and n300s AI-acceleration PCIe cards; a teardown reveals a purpose-built Wormhole ASIC fabric and a board-level design optimized for chip-to-chip Ethernet and GDDR6 memory. Each Wormhole ASIC is a 10×12 logical tile grid containing one ARC tile (PCIe-facing RISC), D tiles that bridge groups of GDDR6 (two 1GB banks per DRAM chip, giving 12GB per ASIC), E tiles that handle 100Gb Ethernet, a PCIe bridge tile, and many T compute tiles. T tiles host five Baby RISC-V cores, 1.5 MB SRAM, a matrix unit (2048 multipliers with 5b×7b ops) and a 32-lane vector unit — the core AI compute resources. The n300s packs two ASICs (each with 12 GB GDDR6) linked by internal 100GbE lanes; the second ASIC has no direct PCIe, so the host talks to it via the first ASIC’s internal Ethernet. Architecturally notable: tiles route over a two-channel NoC (north/east vs west/south) with 32‑byte links (planned 64‑byte in the next-generation Blackhole), and the tile grid logically wraps around with physical interleaving to equalize latencies. Tenstorrent uses manufacturing “harvesting” to disable whole T rows for defect tolerance, which yields 72 usable T tiles on n150s and 64 per ASIC on n300s but produces card-to-card variability in how many T tiles sit adjacent to DRAM — a real factor for low-latency memory-bound workloads. Practically, the design emphasizes scalable on-card networking and dense small-bit matrix math, but I/O limits mean full Ethernet bandwidth needs a larger Galaxy server form factor to be saturated.