Chip designer SiFive aims to cram more RISC-V cores into AI chips (www.theregister.com)

SiFive has announced the second generation of its RISC-V-based Intelligence cores aimed at powering AI accelerators and edge applications such as robotics and IoT devices. Building on its existing success—powering chips for tech giants including Google, Meta, and Microsoft—SiFive’s new X160 and X180 cores support 32-bit and 64-bit architectures respectively, feature clusters of up to four cores, and offer 128-bit vector registers with 64-bit data paths. These cores are designed not for general-purpose computing but as accelerator control units (ACUs) that efficiently feed tensor cores and matrix multiplication units, easing integration and saving customers from costly custom CPU designs. Alongside the X100 series, SiFive has revamped its higher-end X280 and X390 cores with a simplified cache hierarchy that replaces a three-level system with a customizable shared L2 cache, boosting utilization and reducing die area. The X390 Gen 2 core, capable of quadrupling compute and vastly improving data throughput, now supports the RVA23 instruction set, which introduces hardware acceleration for emerging AI-focused data types like BF16 and MXFP8/4 micro-scaling formats—crucial for modern neural network training and inference. SiFive is also enhancing its XM accelerator family with these new cores, enabling scalable AI clusters capable of delivering up to 64 teraFLOPS of FP8 performance per cluster and potentially exceeding 4 petaFLOPS at scale. This strategic push by SiFive to license flexible, RISC-V-based AI accelerator cores represents a major shift towards customizable, open-core architectures in a market dominated by proprietary GPU solutions. By focusing on modular, efficient control cores that complement high-throughput tensor units, SiFive is providing a compelling alternative that could accelerate innovation and reduce dependency on mainstream GPU providers, with first customer silicon expected by Q2 2026.