Documenting an undocumented chip: the TensorCore of TPU v5e (gherkinlabs.com)

A recent exploration has documented the instruction set of Google’s TPU v5e TensorCore, unveiling detailed insights into its architecture and operation. The project, independently conducted by researchers, involved creating a custom driver and running experimental probes on the physical chip to gather vital performance data. This unofficial reference, while not exhaustive, offers a comprehensive overview of the TPU v5e's instruction cycles and functionalities, enhancing the understanding of its scalar and vector processing capabilities. This documentation is significant for the AI/ML community as it provides a clearer understanding of TPU v5e's microarchitecture, relevant for developers and researchers working on machine learning workloads. Key technical details include the TensorCore's operational structure, which features a scalar side for control flow and basic arithmetic, and a vector side for handling complex computations across 128 lanes. The insights gained could improve performance optimizations and guide the development of more efficient software tailored for TPUs, further advancing the efficiency of deep learning models deployed in various AI applications.