SiFive 2nd Gen Intelligence Family Launched – ServeTheHome (www.servethehome.com)

SiFive has unveiled its 2nd Generation Intelligence Family of RISC-V CPUs, designed specifically to address AI workloads with improved efficiency and scalability. This new lineup introduces smaller, lower-power cores alongside enhanced larger IP blocks, enabling a versatile range of applications from lightweight control tasks to heavy AI acceleration. A notable highlight is the inclusion of the X100 small core, optimized as an accelerator control unit to offload tasks from host CPUs, and support for key interfaces like SSCI and VCIX that provide low-latency, high-bandwidth access to CPU registers for scalar and vector processing respectively. Technically, SiFive’s new IP brings significant microarchitectural improvements such as a new exponential function instruction that reduces what used to take 15-22 instructions down to just one, speeding up mathematical operations critical in AI. The pipeline’s loosely coupled scalar-vector design, combined with a configurable VLDQ, effectively hides memory latency in predictable workloads. Replacing its previous L3 cache, SiFive now offers an optional shared 1MB L2 cache to improve cache utilization and free up die area. The family ranges from the 32/64-bit X100 for embedded use, to the higher-performance X280 and X390 cores, culminating in the XM series which integrates four X300 cores with an advanced Gen2 matrix engine for AI acceleration. This launch underscores RISC-V’s growing footprint in AI hardware, providing a flexible, licensable alternative to established architectures like Arm. SiFive’s off-the-shelf IP aims to drive wider adoption of RISC-V in control and accelerator roles, particularly as standards like RVA23 mature to improve software compatibility and ecosystem coherence. With major players like NVIDIA increasingly incorporating RISC-V for control planes, SiFive’s new generation could accelerate the open-source chip movement’s impact on future AI system designs.