Qwenputer: A functioning, deterministic RISC-V CPU inside Qwen3.5 (divagr.com)

Qwenputer, an experimental enhancement of the Qwen 3.5 4B model, has integrated a fully functional RISC-V CPU into its architecture. This innovative design utilizes the model's Gated DeltaNet (GDN) layers as internal RAM, allowing the CPU to execute arithmetic operations and run C and MicroPython code entirely within the model's forward passes without any external tools. Notably, this integration has shown impressive results, outperforming the base Qwen model in various benchmarks, demonstrating its capability to execute a 32-bit RISC-V core that runs independently while maintaining the integrity of the language model. The significance of Qwenputer lies in its potential applications for AI/ML research, particularly in enhancing model interpretability and safety. By utilizing exact control over the RNN layers, it serves as a testbed for developing models that can independently monitor their reasoning processes and potentially avoid CoT monitoring. Furthermore, the integration of a filesystem within the model allows for persistent memory storage across interactions, which could enhance the contextual continuity of language models. As Qwenputer evolves, researchers are excited about its future applications and improvements, including faster execution and the ability to write and run Python within its architecture.