Micron: HBM requires around three times as much wafer area as DDR5 (www.igorslab.de)

Micron recently highlighted the significant manufacturing challenges associated with High Bandwidth Memory (HBM) compared to DDR5 during a presentation at Hot Chips 2026. It revealed that HBM requires roughly three times the wafer area of DDR5 for the same memory capacity due to its design, which features up to 256 memory banks compared to DDR5's 32. This difference in architecture allows HBM to achieve exceptionally high bandwidth—over 2.8 TB/s per stack with the new HBM4—but also means that it demands considerably more silicon resources per bit stored. Consequently, this shift to HBM puts a strain on DRAM manufacturing capacity and influences the entire memory market. The implications of Micron's findings are profound for the AI and machine learning communities, where the performance demands of modern accelerators continue to escalate. The disparity between the rapid growth of computing power and the slower increase in memory bandwidth—termed the "Memory Wall"—highlights a potential bottleneck in data transport for AI workloads. This situation necessitates a continued investment in the development of advanced memory technologies to meet the needs of high-performance computing, suggesting that the memory industry's capacity issues could persist as AI applications proliferate.