Arm A-Profile Architecture developments 2025: Armv9.7-A (community.arm.com)

Arm announced Armv9.7-A, the 2025 update to its A‑Profile ISA, delivering a suite of features targeted at scalability, resource control, AI datatypes and CPU video performance. Key system-level changes include a Domain-based TLB invalidation model that lets software target broadcast invalidations only to cores (or chiplets) where the affected workload ran—cutting invalidation latency in multi‑chiplet/multi‑die systems. Arm also published GICv5 this year, a re‑architected interrupt controller designed for single‑die to multi‑chip systems with improved virtualization efficiency. For resource management and profiling, MPAMv2 extends MPAM with two independent IDs (PARTID and PMG), makes PMGs up to 16 bits, and removes the prior 32‑PARTID virtualization cap by using in‑memory ID translation—enabling system‑wide profiling and flexible virtualization of partitions and monitoring groups. On the AI front, Armv9.7-A adds SVE/SME instructions to natively handle compact 6‑bit datatypes (including the OCP MXFP6 format), reducing memory footprint and bandwidth for ML models. The update also introduces new CPU instructions to accelerate video codecs, acknowledging rising mobile video workloads. Arm is coordinating upstream enablement (Linux/kernel and distros) so these hardware capabilities can be adopted in software stacks and future processors.