Agile Design and Implementation of a Systolic Array-Based CNN Accelerator (2024) [pdf] (www.ijerm.com)

A recent study published in the International Journal of Engineering Research and Management details the development of a flexible convolutional neural network (CNN) accelerator based on a systolic array architecture. Researchers employed an agile design approach using Spinal HDL, a modern hardware description language, to enhance the accelerator's configurability and efficiency. This innovative design allows for a high degree of parallel processing and effective use of on-chip memory, addressing a common limitation in existing FPGA-based accelerators that often cater to specific neural networks. This development is significant for the AI/ML community as it paves the way for more adaptable hardware solutions capable of accelerating various neural network models. The proposed accelerator can generate dedicated neural network designs as plugins through parameter modifications, allowing broader application in both academia and industry. Experimental results indicate that the accelerator can run the YOLOv4-Tiny algorithm at an impressive 85.09 frames per second, achieving notable performance while maintaining low power consumption. This advancement emphasizes the potential of systolic arrays in deep learning applications and the effectiveness of agile methodologies in hardware design.