Hardware-Software Co-Design for Float16 On-Device Training on RISC-V Single-Core (arxiv.org)

Researchers have unveiled an open-source framework for performing on-device training using float16 precision on RISC-V single-core architectures, significantly optimized for resource-constrained environments. By leveraging the Zfh and Zvfh standard RISC-V extensions, this innovative approach reduces the memory footprint by approximately 50% compared to traditional float32 usage, without notably degrading model performance. It also enhances capabilities for transfer learning and fine-tuning through layer-freezing techniques. This development is critical for the AI/ML community as it supports the deployment of deep neural networks (DNNs) on embedded systems with limited computational resources, expanding accessibility to advanced machine learning applications in various industries. The low area overhead associated with implementing Zfh on a RV64GC FPGA softcore, with only minor increases in resource usage, underscores the practicality of this approach. Moreover, by further detailing the architecture of the Zvfh implementation, the framework paves the way for additional customization and scaling of machine learning applications on lower-cost hardware platforms.