Is x86 ready to ACE it? (chipsandcheese.com)

Intel's x86 Ecosystem Advisory Group has announced the ACE instruction set architecture extension, designed to complement the existing AMX extension for enhanced matrix multiplication in machine learning applications. ACE introduces a new accelerator type that streamlines operations by using fixed tile sizes while also supporting FP8 data types, marking a shift from the previous support of complex numbers in AMX. This development indicates a broader adaptation of CPU designs to meet the demands of AI workloads, enabling more efficient processing without relying solely on traditional GPU architectures. The technical implications of ACE are significant, particularly its outer product approach, which may enhance performance in matrix multiplications compared to the inner product methods employed by its AMX predecessor. Moreover, ACE's integration of a 1024-bit Block Scale Register allows for better management of low precision data types like FP8, addressing dynamic range concerns typical in AI models. This flexibility in handling various quantized weights and efficient memory usage, combined with the introduction of new instructions for data conversion, positions ACE as a potent tool that highlights the continuous evolution of CPU architectures in the AI/ML landscape.