FP64 Floating-Point Emulation in INT8 (arxiv.org)

Researchers have demonstrated and analyzed an extreme mixed-precision approach: emulating IEEE FP64 using split-integer techniques running entirely on fixed‑point (INT8) tensor‑core units. The paper evaluates the practicality of this FP64-in-INT8 emulation for decompositional factorizations and dense linear solvers, running extensive numerical tests and scaled input-size experiments on NVIDIA Hopper GPUs. The study catalogs new failure modes and accuracy degradations that arise when very low-level fixed-point arithmetic is used to mimic double precision, and highlights how matrix entry range and problem scaling strongly influence error growth and stability. This work matters to the AI/ML community because it explores the performance/energy upside of using ubiquitous low‑precision accelerators for traditionally double-precision tasks—relevant to large-scale training, inference for physics-informed models, and scientific ML—while quantifying the numerical risks. Key technical takeaways: split‑integer FP64 emulation can yield substantial throughput gains but introduces overflow/underflow, increased rounding bias, and conditioning-dependent error amplification; errors correlate with matrix value ranges and input size; and practical deployment needs careful input scaling, compensated algorithms, or algorithmic redesign (e.g., mixed-precision-aware factorization and error correction). The results suggest promising performance opportunities but also a clear need for algorithm/hardware co-design and robust numerical safeguards before replacing true FP64 in sensitive workloads.