IBM says it can fit nearly 100B transistors on a chip (www.zdnet.com)

IBM has announced its groundbreaking sub-1-nanometer NanoStack architecture, which can accommodate nearly 100 billion transistors on a chip, marking a significant leap in semiconductor technology. This innovation is pivotal for the AI/ML community as it promises to deliver chips that are both cheaper to run and more powerful than current models, addressing the growing demand for low-power, high-efficiency processors in data centers. The NanoStack technology, introduced as part of a research project ahead of VLSI 2026, features a 3D design that effectively doubles transistor density compared to IBM's previous 2-nm test chip. The implications of this new architecture are profound. Not only does it offer up to 50% higher performance or 70% lower power consumption for equivalent performance compared to current chips, but it also presents a 40% improvement in SRAM cell area scaling—critical for supporting AI applications that rely heavily on memory bandwidth. IBM aims for NanoStack to evolve into the next leading-edge architecture, eventually replacing existing nanosheet technology, with a pathway to commercialization within the next five years. This advancement could significantly enhance the performance-per-watt metrics for AI workloads, driving industry-wide shifts in how computing can support AI's skyrocketing requirements.