Our edge AI compiler outperforms Google and vendor toolchains (deepgate.ai)

A new AI compiler, DeepGate (v0.15.0), has been launched, claiming significant performance improvements over established tools like Google’s TensorFlow Lite for Microcontrollers (TFLM) and various vendor-specific toolchains. DeepGate optimizes quantized .tflite models for microcontrollers, showing up to 3× less RAM usage and up to 2× faster inference on Arm Cortex-M devices. The compiler has been validated through the MLPerf Tiny v1.4 benchmark across multiple silicon vendors, outperforming TFLM and vendor tools (e.g., Analog Devices, Infineon, and Silicon Labs). Notably, DeepGate enabled models that previously could not fit into memory, broadening application potential in constrained edge environments. The significance of DeepGate lies in its ability to tackle efficiency challenges essential for edge AI, where power constraints and real-time processing are critical. The compiler leverages static binary compilation, advanced memory planning at compile time, and custom hardware-aware optimizations, deviating from TFLM's runtime interpretation approach. Future developments aim to enhance support for sparse networks, lower-bit quantization, and more efficient attention mechanisms in Transformer models, positioning DeepGate as a promising solution for high-performance edge AI applications in increasingly resource-limited settings.