CPPL: A Circuit Prompt Programming Language (arxiv.org)

Researchers have introduced CPPL, a novel programming language designed to improve the integration of large language models (LLMs) in hardware design, specifically at the register-transfer level (RTL). Traditional RTL generation is complex, often resulting in difficulties related to validation and optimization. The significance of CPPL lies in its ability to transform LLM-assisted hardware generation into a statically checkable problem, addressing limitations around current LLMs that struggle with the intricacies of compiler IR syntax and the strict demands of hardware design. CPPL features a Python frontend domain-specific language (DSL) for outlining module interfaces, paired with a JSON-based circuit intermediate representation (IR) that is accessible to both compilers and LLMs. This design allows the compiler to automatically infer operation widths and validate generated IR, ensuring that output aligns with backend optimization directives. In tests against the RTLLM benchmark, CPPL demonstrated increased functional correctness compared to traditional methods and showed that the subsequent optimization through CIRCT significantly reduces the complexity of synthesizable Verilog output. This innovation paves the way for more reliable and analyzable hardware designs leveraging LLMs, enhancing the prospects of AI integration in hardware development.