TSMC SoIC 3D stacking roadmap outlines path from 6-micron pitches to 4.5 in 2029 (www.tomshardware.com)

TSMC has unveiled an ambitious roadmap for its System on Integrated Chips (SoIC) 3D stacking technology, aiming to enhance the efficiency of chip packaging for advanced AI and high-performance computing (HPC) applications. At its recent North American Technology Symposium, the company announced plans to scale down interconnect pitches from 9 microns in 2023 to 4.5 microns by 2029. This development is particularly significant as it transitions from face-to-back (F2B) to face-to-face (F2F) stacking, allowing for more direct signal pathways that significantly reduce latency and energy consumption while exponentially increasing signal density—from 1,500 to 14,000 signals per mm². With both F2B and F2F stacking now within reach, TSMC anticipates a rapid acceleration in technology adoption, particularly among major clients like Broadcom, who will utilize the new F2F architecture for advanced processors like Fujitsu's Monaka supercomputer CPU. This system highlights how cutting-edge 3D integration can combine multiple chiplets to achieve superior performance and density, addressing the industry's need for innovative packaging solutions as traditional transistor scaling slows. As TSMC's SoIC technology matures, it positions itself as a crucial driver for future advancements in AI and computing, marking a pivotal shift in how high-performance chips are designed and manufactured.