System Design for AI Engines in FPGA (www.hackster.io)

AMD/Versal system-design tutorial: the author demonstrates a Vitis Unified heterogeneous flow for Versal devices (targeting VCK190) that integrates AIE/AIE-ML engines, HLS and RTL IP to build AI/ML and DSP pipelines. Using Vitis and Vivado 2025.1 plus PetaLinux 2025.1, the project shows how to start from AMD’s GitHub reference platform and iterate between Vitis and Vivado—creating a Vitis Sub System (VSS), exporting a Vitis Metadata Archive (VMA), re-importing into Vivado for optimization, and finally building a fixed Vitis platform with embedded Linux applications. License prerequisites (AI Engine Tools and Vitis HLS) are highlighted. Key technical workflow and implications: the tutorial scripts automate stages—make vivado_platform, make vss, make vitis_ip, make vma_export, make vivado_fixed, make vitis_platform, make ps_apps and make package—producing an XSA and SD-card image that boots on the VCK190 and runs an AIE test (./aie_dly_test.exe my.xclbin 512). It covers practical details like AXI/NoC/CIPS integration, clocks exposed to the Vitis linker (500 MHz down to 62.5 MHz), interrupts, and AIE simulation/analysis for throughput estimation. The approach underlines the power of co-design: combining AIE graphs, HLS kernels and RTL within a single flow to accelerate AI/DSP workloads on Versal, and enables iterative optimization by moving between Vitis and Vivado.