Design tackles integer factorization through digital probabilistic computing (techxplore.com)

Northwestern researchers have built a digital, synchronous probabilistic Ising machine (PIM) on a custom ASIC that uses voltage-controlled magnetic tunnel junctions (V‑MTJs) as a compact, high‑throughput entropy source and demonstrated it on integer factorization tasks. Instead of analog or magnetics-heavy front ends used in prior PIM prototypes, their design implements bistable probabilistic bits (p‑bits) in CMOS logic and reads randomized bit sequences from an adjacent V‑MTJ chip; the network’s engineered energy minimum corresponds to the correct factorization. The prototype was fabricated on a 130 nm foundry node and published in Nature Electronics (2025). This advance matters because it shows a scalable, manufacturable path for probabilistic computing that avoids area‑hungry digital‑to‑analog interfaces and leverages standard CMOS design flows. V‑MTJs proved robust to device variation and can be integrated on‑chip in future nodes, enabling dense arrays of p‑bits with synchronous clocking for controlled updates. While the team used factorization as a clear test with a unique verifiable solution, the architecture generalizes to combinatorial optimization and other NP‑hard problems—potentially offering energy‑efficient accelerators for optimization workloads if scaled and integrated into advanced processes.