Building an Open-Source Verilog Simulator with AI: 580K Lines in 43 Days (normalcomputing.com)

A Normal engineer has successfully developed an open-source Verilog simulator using AI agents within just 43 days, resulting in a staggering 580,000 lines of code added to a fork of the CIRCT project. This simulator features a comprehensive verification stack, including an event-driven simulator, integration with VPI/cocotb, and support for mutation and formal verification. The rapid development process showcased the potential of AI in tackling well-defined engineering challenges, bridging the critical gap between compiling Verilog and simulating real-world designs—a task traditionally viewed as too complex for small teams. This achievement is significant for the AI and machine learning community as it demonstrates that AI can significantly reduce development time for complex tools in the electronic design automation (EDA) space, a sector typically dominated by expensive commercial solutions. The work not only adds to the open-source ecosystem but also challenges the long-held belief that building verification tools requires extensive resources and time. Key technical innovations included optimizing the simulator for real-world protocol testbenches and improving performance through Just-In-Time compilation techniques. The experiment highlights the capability of AI to transform EDA workflows, possibly leading to a future with more accessible verification tools.