Ripple: Asynchronous Programming for Spatial Dataflow Architectures (dl.acm.org)

Ripple presents a purpose-built FPGA architecture and tool approach for efficiently prototyping asynchronous (clockless) dataflow logic on spatial hardware. Rather than forcing event-driven, non-blocking programs into synchronous clock domains, Ripple provides fabric primitives and a mapping flow that express low-level application behavior as asynchronous dataflow—handshaked channels, token-passing computation, and fine-grained concurrency—so designers can implement genuinely clockless designs directly on reconfigurable silicon. The paper argues this reduces the impedance mismatch between asynchronous semantics and synchronous FPGAs, enabling higher throughput, lower dynamic power, and more natural implementations of streaming/event-driven kernels. For the AI/ML community, Ripple matters because many modern accelerators and streaming inference pipelines are naturally dataflow- and event-driven; evaluating clockless implementations can reveal benefits in latency, energy, and scalability that synchronous designs miss. Technically, Ripple tackles mapping, routing and primitive support (handshake channels, storage elements, and composable dataflow operators) so asynchronous abstractions compile efficiently to spatial resources. That combination—architectural support plus a mapping flow—lowers the barrier to experiment with delay-insensitive and handshake-based circuits, making it easier to explore novel ML accelerator microarchitectures and runtime trade-offs driven by data-dependent execution.