Show HN: Low-rank approximation for 3x3 FPGA convolutions (33% less DSP usage) (www.dockerr.blog)

A recent innovation in hardware-efficient algorithms promises to revolutionize FPGA-based computing for space applications, drones, and edge AI systems by reducing matrix multiplication complexity by 33% while maintaining over 99% accuracy. The challenge addressed is the heavy resource demand of DSP blocks in FPGAs, particularly when processing 3x3 convolution kernels, which are fundamental to computer vision tasks. Traditional methods are impractical for hardware implementations due to high precision requirements and complexity. Instead, this new approach leverages a machine-learning-driven search for low-rank coefficients, enabling a reduction in multiplications from three to two for dot products through simple bit-shifting and addition operations, minimizing energy consumption and power budget. The implications are significant: users can expect lower power usage and weight, crucial for missions where every watt and gram count. For example, satellites could achieve higher resolution imaging with the same power budget, while drones could benefit from extended flight times and improved processing capabilities. Although the algorithm sacrifices some numerical precision, its performance on CNNs remains strong, making it well-suited for visual perception tasks. The open-source nature of the project means it can be widely adopted, fostering further innovation in resource-constrained environments and underscoring the importance of co-designing algorithms tailored to hardware capabilities in advancing AI/ML applications.