Nvidia wants 10Gbps HBM4 to blunt AMD's MI450, report claims (www.tomshardware.com)

Reportedly ahead of its 2026 Vera Rubin GPU launch, Nvidia has asked HBM vendors to push HBM4 per-pin speeds from JEDEC’s 8Gb/s baseline to 10Gb/s — a move intended to widen per‑GPU memory bandwidth and blunt AMD’s upcoming MI450/Helios push. At 10Gb/s a 2,048‑bit HBM4 stack delivers about 2.56 TB/s (vs ~2 TB/s at 8Gb/s), so six stacks would clear ~15 TB/s per GPU and help Rubin CPX hit very high rack-level inference throughput targets (Nvidia advertises ~1.7 PB/s on a full NVL144 rack). For AI/ML workloads that are memory‑bandwidth bound, that extra headroom can translate directly into higher model inference and data‑feed performance. Technically, 10Gb/s I/O raises power, timing margin, and substrate/base‑die stress, so Nvidia may need to segment Rubin SKUs (10Gb/s for CPX, lower speed for standard Rubin) or accept staggered supplier qualification to protect yields. SK hynix claims HBM4 readiness and “over 10Gb/s” capability; Samsung is moving its HBM4 base die to 4nm FinFET to reduce switching power and support higher clocks; Micron is sampling 2,048‑bit HBM4 but hasn’t confirmed 10Gb/s. The tradeoffs matter for the AI ecosystem: higher bandwidth can boost large-model inference, but supplier variation, yield, thermal and rack‑level power constraints could limit availability, cost-effectiveness, and real‑world performance gains.