An MLIR Lowering Pipeline for Stencils at Wafer-Scale (arxiv.org)

A new machine learning intermediate representation (MLIR) pipeline has been developed to optimize stencil-based computations for the Cerebras Wafer-Scale Engine (WSE), which boasts over 900,000 compute units interconnected on a single wafer. This pipeline aims to automatically target the unique asynchronous execution model of the WSE without necessitating changes to existing application-level code. By leveraging domain-specific information about stencils, traditionally used in high-performance computing (HPC), the compiler transforms these computations into highly efficient Code for the WSE. This advancement is significant for the AI and ML community as it provides an efficient way to utilize the immense capabilities of the WSE for HPC applications, previously requiring extensive manual optimizations. The proposed method demonstrates performance on the WSE3 that is around 14 times faster than a cluster of 128 Nvidia A100 GPUs and up to 20 times quicker than a Cray-EX supercomputer with 128 CPU nodes, showcasing the potential of streamlined compiler advancements to enhance processing speed and efficiency in complex computations.