TinyTinyTPU: 2×2 systolic-array TPU-style matrix-multiply unit deployed on FPGA (github.com)

The TinyTinyTPU project has announced the deployment of a compact 2×2 systolic-array TPU-style matrix-multiply unit, designed for educational purposes and implemented in SystemVerilog on an FPGA. This minimalistic architecture includes a fully functional TPU setup with features like a post-MAC pipeline, UART-based interface, and the ability to perform multi-layer MLP inference on a Basys3 FPGA board, utilizing around 1,000 LUTs and Flip-Flops each, and approximately 25,000 gates. The project aims to teach TPU architecture principles and facilitate FPGA prototyping. This initiative is significant for the AI/ML community as it simplifies the understanding of systolic array data flows—where data and partial sums traverse in different orientations—while providing a practical platform for small-scale machine learning tasks. The TinyTinyTPU implements both the diagonal wavefront weight loading technique and a complete multi-layer inference pipeline, allowing for sequential processing with double-buffered activations. By making this technology open-source, the project encourages experimentation and further development within the community, paving the way for more robust TPU architectures and eventually scaling to larger models, similar to Google's TPU v1.